Phase-locked loop (PLL) circuitry may be used to generate and control one or more clock signals to be propagated throughout an integrated circuit (IC). In system-on-a-chip (SOC) and other IC applications, such PLLs have limited lockable frequency ranges. To allow PLLs to lock despite such limited lockable frequency ranges, a frequency of a reference clock can be provided to the PLL upon power-up or initialization to facilitate locking onto the reference clock for generation of output PLL clocks.
Many ICs also support a number of different reference clock frequencies. In one example, as many as ten different frequencies can be accommodated by a single IC (e.g., an SOC). Some approaches include the use of four strap pins to encode the different reference clock frequencies. In such approaches, the SOC, IC and/or application can be programmed to support a particular reference clock frequency. However, the strap pin approach has drawbacks including increased printed-circuit board (PCB) space since one or more additional external resistor(s) are required, greater on-chip real estate for input buffer, electrostatic discharge (ESD), decoder, and other associated circuitry, and a resultant increase in costs.